This invention relates to a method for manufacturing an integrated semiconductor device which can achieve ultra high speed operation.
To accomplish high speed operation, there is utilized a bipolar type semiconductor device such as an ECL/CML (Emitter Coupled Logic/Current Mode Logic).
In the ECL/CML type circuit, operational speed is mainly determined by a parastic capacitance accompanied with mutual interconnections between elements which constitute the circuit and a base resistance multiplied by a gain-bandwidth product of a transistor.
The most effective way to reduce the parastic capacitance is to shrink a base area so that a junction capacitance, which influences greatly the operational speed, is provided between a base and a collector of a transistor.
On the other hand, to reduce the parastic capacitance generated by the interconnection resistance, there is usually provided a structure in which resistors made of poly crystaline silicon are formed on a thick isolating oxide film.
To achieve reduction of the base resistance, it is necessary to reduce the resistance of an active base layer beneath an emitter by adjoining a low resistivity inactive base to the emitter and by shrinking the emitter width.
The gain-bandwidth product can be improved by reducing the junction capacitances between an emitter and a base and between a base and a collector by shrinking their planar scales, and it is further effective to shrink a vertical scale by shallowing base and emitter junctions or reducing a thickness of a collector epitaxial layer.
Among typical self-alignment techniques available to achieve high speed operation with gate delay time being less than 100 ps/gate, those of the following three articles are currently well-known:
(1) T. Sasaki et al. Electronics Letters, 14th April 1983 vol. 19 No. 8 P 283-284
(2) N. Ohuchi et al. IEDM Techinical Digest, 1983 P 55-58
(3) T. Nakamura et al. ISSCC Technical Digest, 1981 P 214-215, 274
These three techniques, although they differ from each other in transistor structure and manufacturing method, commonly employ a structure wherein a base electrode is disposed outside the element area by using poly crystaline silicon so that the base resistance can be reduced by shrinking the base region to reduce the junction capacitance between the base and the emitter and by adjoining a low resistivity poly crystaline silicon electrode to the emitter.
In other words, it is inevitably necessary to optimumly design the base structure when a high speed transistor is required.
The conventional proposed base structures of high speed bipolar transistor can be classified into two groups:
The first group is disclosed in the above articles (1) and (2) wherein there are provided an external base region with low resistivity to reduce the base resistance and a pull-out electrode made of poly crystaline silicon located above the external base region and adjucent to the emitter.
In this case, the external base region area should be formed as small as possible to prevent increase of the junction capacitance between the base and the collector.
This structure can be achieved by a relatively simplified process and also can realize both reduction of the base resistance and shrinkage of the base area.
On the other hand, the technique described in the article (3) relates to a method to realize an ideal structure having no external base by pulling out the base electrode made of buried poly crystaline silicon from a side wall of the active base.
According to this technique, there exists almost no external base region so that the base-collector junction is constituted only by the active base region with low impurity concentration whereby both the junction capacitance between the base and the collector and the base resistance are tremendously reduced.
The former technique, still requires the external base, though there is the advantage that the process is relatively simple, which restricts the reduction of the junction capacitance between the base and the collector.
The latter technique, though it provides an ideal base structure mostly suitable for high speed operation, requires complicated manufacturing processes to form the buried poly crytaline silicon electrode which generates induced defects in a selective oxidizing process and makes it difficult to form a poly crystaline silicon electrode with reproducibility.